1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit capable of reducing test time.
2. Related Art
Generally, in semiconductor integrated circuits, one mat is selected when a burn-in test (or normal test) is carried out. Word lines which are correspondent to the selected mat are enabled and then a read or write test is carried out.
Recently, in the semiconductor integrated circuits, the test is carried out by enabling row and column address signals independently for all the cells. Therefore, the test time is increased so that the cost is also increased.
Accordingly, in order to reduce the test time, it is required to provide a test circuit that is capable of simultaneously carrying out an active-related test (for example, a test to activate a plurality of word lines) and a read/write-related test (for example, a test to activate a plurality of sense amplifiers) with activating a plurality of mats.